Today's computing systems support various power saving techniques including moving the processor and the computing system through various hardware P-states and C-states. Many of these techniques include determining processor utilization level over a time window and then select a frequency, which may match the processor utilization level. These techniques cause the frequency of the clock signal supplying the processor cores to be reduced in response to a low processor utilization level.
However, changing the frequency of the clock signal based only on the processor utilization level may, at times, impact the performance of some activities. For example, the frequency of the clock signal may be lowered if the processor utilization is low, however, a high performance activity may occur within that window of low processor utilization. These techniques may still continue to process the high performance activity at the same low frequency level thus impacting performance.